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1 of 16 note: some revisions of this device may incorporate devi ations from published specifications known as errata. multiple revisions of any device may be simultaneously available through various sales channels. for information about device errata, click here: www.maxim - ic.com/errata . features ? integrated nv sram, real - time clock (rtc), crystal, power - fail control circuit, and lithium energy source ? clock registers are accessed identically to the static ram. these registers are resident in the eight top ram locati ons ? century byte register (y2k compliant) ? totally nonvolatile with over 10 years of operation in the absence of power ? bcd - coded century, year, month, date, day, hours, minutes, and seconds with automatic leap year compensation valid up to the year 2100 ? bat tery voltage - level indicator flag ? power - fail write protection allows for 10% v cc power - supply tolerance ? lithium energy source is electrically disconnected to retain freshness until power is applied for the first time ? dip module only: standard jedec byte - w ide 512k x 8 static ram pinout ? powercap module board only: surface - mountable package for direct connection to powercap containing battery and crystal replaceable battery (powercap) power - on reset output pin - for - pin compatible with other densities of ds174x p timekeeping ram ? also available in industrial temperature range: - 40c to +85c pin configurations 19 - 5504; rev 3 /1 2 ds1747/ds1747p y2k - compliant, nonvolatile timekeeping rams a17 a18 13 1 2 3 4 5 6 7 8 9 10 11 12 14 31 encapsulated dip (512k x 8) a14 a7 a5 a4 a3 a2 a1 a0 dq1 dq0 v cc a15 we a13 a8 a9 a11 oe a10 ce dq7 dq5 dq6 32 30 29 28 27 26 25 24 23 22 21 19 20 a16 a12 a6 dq2 gnd 15 16 18 17 dq4 dq3 maxim ds1747 1 n.c. 2 3 a15 a16 rst v cc we oe ce dq7 dq6 dq5 dq4 dq3 dq2 dq1 dq0 gnd 4 5 6 7 8 9 10 11 12 13 14 15 16 17 a17 a14 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 34 a18 x1 gnd v bat x2 powercap module board (uses ds9034pcx + or ds9034i - pcx+ powercap) maxim ds1747p top view
ds1747/ds1747p y2k - compliant, nonvolatile timekeeping rams 2 of 16 pin description 2b pin 0 b name 3b function edip powercap 1 34 a18 address input 2 3 a16 3 32 a14 4 30 a12 5 25 a7 6 24 a6 7 23 a5 8 22 a4 9 21 a3 10 20 a2 11 19 a1 12 18 a0 23 28 a10 25 29 a11 26 27 a9 27 26 a8 28 31 a13 30 33 a17 31 2 a15 13 16 dq0 data input/output 14 15 dq1 15 14 dq2 17 13 dq3 18 12 dq4 19 11 dq5 20 10 dq6 21 9 dq7 16 17 gnd ground 22 8 ce active - low chip - enable input 24 7 oe active - low output - enable input 29 6 we active - low write - enable input 32 5 v cc power - supply input 1 n.c. no connection 4 1b rst active - low power - on reset output (see pin co nfiguration) x1, x2 crystal input, output connections (see pin configuration ) v bat battery connection
ds1747/ds1747p y2k - compliant, nonvolatile timekeeping rams 3 of 16 ordering information part supply voltage (v) temp range pin - package top mark ? ds1747 - 70+ 5.0 0c to +70c 32 edip (0.740a) ds1747 - 70 + ds1747 - 70i nd+ 5.0 - 40c to +85c 32 edip (0.740a) ds1747 - 70ind + ds1747p - 70+ 5.0 0c to +70c 34 powercap* ds1747p + 70 ds1747p - 70ind+ 5.0 - 40c to +85c 34 powercap* ds1747p + 70 ind ds1747w - 120+ 3.3 0c to +70c 32 edip (0.740a) ds1747w - 120 + ds1747w - 120ind+ 3.3 - 40 c to +85c 32 edip (0.740a) ds1747w - 120ind + ds1747wp - 120+ 3.3 0c to +70c 34 powercap* ds1747wp + 120 ds1747wp - 120ind+ 3.3 - 40c to +85c 34 powercap* ds1747wp + 120 ind + denotes a lead(pb) - free/rohs - compliant package. * ds9034pcx+ or ds9034i - pcx + required (must be ordered separately). ? a + indicates lead (pb )- free. the top mark will include a + symbol on lead (pb)- free devices. description the ds1747 is a full - function, year - 2000- compliant (y2kc), real - time clock/calendar (rtc) and 512k x 8 nonvolati le static ram. user access to all registers within the ds1747 is accomplished with a byte - wide interface as shown in figure 1. the rtc information and control bits reside in the eight uppermost ram locations. the rtc registers contain century, year, month, date, day, hours, minutes, and seconds data in 24 - hour binary - coded decimal (bcd) format. corrections for the date of each month and leap year are made automatically. the rtc clock registers are double buffered to avoid access of incorrect data that can o ccur during clock update cycles. the double - buffered system also prevents time loss as the timekeeping countdown continues unabated by access to time register data. the ds1747 also contains its own power - fail circuitry that deselects the device when the v cc supply is in an out - of - tolerance condition. this feature prevents loss of data from unpredictable system operation brought on by low v cc as errant access and update cycles are avoided.
ds1747/ds1747p y2k - compliant, nonvolatile timekeeping rams 4 of 16 figure 1 . block diagram packages the d s1747 is available in two packages (32 - pin dip and 34 - pin powercap module). the 32 - pin dip style module integrates the crystal, lithium energy source, and silicon all in one package. the 34 - pin powercap module board is designed with contacts for connection to a separate powercap (ds9034pcx) that contains the crystal and battery. this design allows the power - cap to be mounted on top of the ds1747p after the completion of the surface mount process. mounting the powercap after the surface mount process prevent s damage to the crystal and battery due to the high temperatures required for solder reflow. the powercap is keyed to prevent reverse insertion. the powercap module board and powercap are ordered separately and shipped in separate containers. the part numb er for the powercap is ds9034pcx. time and date operations the contents of the time and date registers are in bcd format. the day - of - week register increments at midnight. values that correspond to the day of week are user - defined, but must be sequential ( i.e., if 1 equals sunday, then 2 equals monday and so on). illogical time and date entries result in undefined operation. clock operations reading the clock while the double - buffered register structure reduces the chance of reading incorrect data, interna l updates to the ds1747 clock registers should be halted before clock data is read to prevent reading of data in transition. however, halting the internal clock register updating process does not affect clock accuracy. updating is halted when a one is writ ten into the read bit, bit 6 of the century register (see table 2). as long as a one remains in that position, updating is halted. after a halt is issued, the registers reflect the count, that is day, date, and time that was current at the moment the halt command was issued. however, the internal clock registers of the double - buffered system continue to update so that the clock accuracy is not affected by the access of data. all the ds1747 registers are updated simultaneously after the internal clock regist er updating process has been re - enabled. updating is within a second after the read bit is written to zero. the read bit must be set to a zero for a minimum of 500 s to ensure the external registers will be updated. maxim ds1747
ds1747/ds1747p y2k - compliant, nonvolatile timekeeping rams 5 of 16 table 1 . truth table v cc ce oe we mode dq power v cc >v pf v ih x x deselect high - z standby v il x v il write data in active v il v il v ih read data out active v il v ih v ih read high - z active v so ds1747/ds1747p y2k - compliant, nonvolatile timekeeping rams 6 of 16 table 2 . register map address data function range b7 b6 b5 b4 b3 b2 b1 b0 7ffff 10 year year year 00 - 99 7fffe x x x 10 month month month 01 - 12 7fffd x x 10 date date date 01 - 31 7fffc bf ft x x x day day 01 - 07 7ff fb x x 10 hour hour hour 00 - 23 7fffa x 10 minutes minutes minutes 00 - 59 7fff9 osc 10 seconds seconds seconds 00 - 59 7fff8 w r 10 century century century 00 - 39 osc = stop bit r = read bit ft = frequency test w = write bit x = see note bf = battery flag note: all indicated x bits are unused, but must be set to 0 during write cycles to ensure proper clock operation. retrieving data from ram or clock the ds1747 is in the read mode whenever oe (output enable) is low, we (write enable) is high, and c e (chip enable) is low. the device architecture allows ripple - through access to any of the address locations in the nv sram. valid data will be available at the dq pins within t aa after the last address input is stable, providing that the ce and oe access times and states are satisfied. if ce or oe access times and states are not met, valid data will be available at the latter of chip - enable access (t cea ) or at output enable access time (t oea ) . the state of the data input/output pins (dq) is controlled by c e and oe . if the outputs are activated before t aa , the data lines are driven to an intermediate state until t aa. if the address inputs are changed while ce and oe remain valid, output data will remain valid for output data hold time (t oh ) but will then go indeterminate until the next address access. writing data to ram or clock the ds1747 is in the write mode whenever we , and ce are in their active state. the start of a write is referenced to the latter occurring transition of we or ce . the addresses must be held valid throughout the cycle. ce or we must return inactive for a minimum of t wr prior to the initiation of another read or write cycle. data in must be valid t ds prior to the end of write and remain valid for t dh afterward. in a typical application, the oe signal will be high during a write cycle. however, oe can be active provided that care is taken with the data bus to avoid bus contention. if oe is low prior to we transitioning low the data bus can become active with read data defined by the addre ss inputs. a low transition on we will then disable the output t wez after we goes active.
ds1747/ds1747p y2k - compliant, nonvolatile timekeeping rams 7 of 16 data - retention mode the 5v device is fully accessible and data can be written or read only when v cc is greater than v pf . however, when v cc is below the power failing point, v pf , (point at which write protection occurs) the internal clock registers and sram are blocked from any access. at this time the power fail reset output signal ( rst ) is driven active and will remain active until v cc returns to nominal levels. when v cc falls below the battery switch point v so (battery supply level), device power is switched from the v cc pin to the backup battery. rtc operation and sram data are maintained from the battery until v cc is returned to nominal levels. the 3.3v device is f ully accessible and data can be written or read only when v cc is greater than v pf . when v cc falls below the power fail point, v pf , access to the device is inhibited. at this time the power fail reset output signal ( rst ) is driven active and will remain act ive until v cc returns to nominal levels. if v pf is less than v so , the device power is switched from v cc to the backup supply (v bat ) when v cc drops below v pf . if v pf is greater than vso , the device power is switched from v cc to the backup supply (v bat ) when v cc drops below v so . rtc operation and sram data are maintained from the battery until v cc is returned to nominal levels. the rst signal is an open drain output and requires a pull up. except for the rst , all control, data, and address signals must be pow ered down when v cc is powered down. battery longevity the ds1747 has a lithium power source that is designed to provide energy for clock activity, and clock and ram data retention when the v cc supply is not present. the capability of this internal power s upply is sufficient to power the ds1747 continuously for the life of the equipment in which it is installed. for specification purposes, the life expectancy is 10 years at +25 c with the internal clock oscillator running in the absence of v cc power. each d s1747 is shipped from maxim with its lithium energy source disconnected, guaranteeing full energy capacity. when v cc is first applied at a level greater than v pf , the lithium energy source is enabled for battery backup operation. actual life expectancy of the ds1747 will be much longer than 10 years since no lithium battery energy is consumed when v cc is present. battery monitor the ds1747 constantly monitors the battery voltage of the internal battery. the battery flag bit (bit 7) of the day register is u sed to indicate the voltage level range of the battery. this bit is not writable and should always be a one when read. if a zero is ever present, an exhausted lithium energy source is indicated and both the contents of the rtc and ram are questionable.
ds1747/ds1747p y2k - compliant, nonvolatile timekeeping rams 8 of 16 absolute maximum ratings voltage range on any pin relative to ground 5.5v version . - 0.3v to +6.0v 3.3v version. - 0.3v to +4.6v operating temperature range (noncondensing) commercial ... ... .................................................................... 0c to +70c industrial .. . - 40c to +85c storage temperature range edip ....................... ... - 40c to +85c powercap .................................................................................................................... ....... - 55c to +125c lead temperature ( soldering , 10s) .......................... .. . ..+260c note: edip is hand or wave - soldered only. soldering temperature ( reflow, powercap) .................................................................................................. +260c this is a stress rating only and functional operation of the devi ce at these or any other condition above those indicated in the operation sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods of time ma y affect device reliability. recommended dc operating co nditions (t a = over the operating range) parameter symbol min typ max units notes logic 1 voltage all inputs v cc = 5v 10% v ih 2.2 v cc + 0.3v v 1 v cc = 3.3v 10% v ih 2.0 v cc + 0.3v v 1 logic 0 voltage all inputs v cc = 5v 10% v il - 0.3 +0.8 v 1 v cc = 3.3v 10% v il - 0.3 +0.6 v 1 dc electrical characteristics (v cc = 5.0v 10%, t a = over the operating range.) parameter symbol min typ max units notes active supply current icc 85 ma 2, 3 , 10 ttl standby current ( ce = v ih ) icc 1 6 ma 2, 3 cmos standby current ( ce v cc - 0.2v) icc 2 4 ma 2, 3 input leakage current (any input) i il - 1 +1 a output leakage current (any output) i ol - 1 +1 a output logic 1 voltage (i out = - 1.0ma) v oh 2.4 1 output log ic 0 voltage (i out = +2.1ma) v ol 0.4 1 write protection voltage v pf 4.25 4.50 v 1 battery switchover voltage v so v bat 1, 4
ds1747/ds1747p y2k - compliant, nonvolatile timekeeping rams 9 of 16 dc electrical characteristics ( v cc = 3.3v 10% , t a = over the operating range.) parameter symbol min typ max units notes active supply current icc 30 ma 2, 3 , 10 ttl standby current ( ce = v ih ) icc 1 2 ma 2, 3 cmos standby current ( ce v cc - 0.2v) icc 2 2 ma 2, 3 input leakage current (any input) i il - 1 +1 a output leakage current (any output) i ol - 1 +1 a output logic 1 voltage (i out = - 1.0ma) v oh 2.4 1 output logic 0 voltage (i out = +2.1ma) v ol 0.4 1 write protection voltage v pf 2.80 2.97 v 1 battery switchover voltage v so v bat or v pf v 1, 4 ac characteri stics read cycle (5v) (v cc = 5.0v 10%, t a = over the operating range.) parameter symbol min typ max units notes read cycle time t rc 70 ns address access time t aa 70 ns ce to dq low - z t cel 5 ns ce e acc ess time t cea 70 ns ce data off time t cez 25 ns oe to dq low - z t oel 5 ns oe access time t oea 35 ns oe data off time t oez 25 ns output hold from address t oh 5 ns
ds1747/ds1747p y2k - compliant, nonvolatile timekeeping rams 10 of 16 ac characteristics read cycle (3.3v) (v cc = 3.3v 10%, t a = over the operating range.) parameter symbol min typ max units notes read cycle time t rc 120 ns address access time t aa 120 ns ce to dq low - z t cel 5 ns ce e access time t cea 120 ns ce data off time t cez 40 ns oe to dq low - z t oel 5 ns oe access time t oea 100 ns oe data off time t oez 35 ns output hold from address t oh 5 ns read cycle timing diagram
ds1747/ds1747p y2k - compliant, nonvolatile timekeeping rams 11 of 16 ac characteristics write cycle (5v) (v cc = 5.0v 10%, t a = over the operating range.) parameter symbol min typ max units notes write cycle time t wc 70 ns address set up time t as 0 ns we pulse width t wew 50 ns ce pulse width t cew 60 ns data setup time t ds 30 ns data hold time t dh1 0 ns 8 data hold time t dh2 0 ns 9 address hold time t ah1 5 ns 8 address ho ld time t ah2 5 ns 9 we data off time t wez 25 ns write recovery time t wr 5 ns ac characteristics write cycle (3.3v) (v cc = 3.3v 10%, t a = over the operating range.) parameter symbol min typ max units notes write cycle time t wc 120 ns address setup time t as 0 120 ns we pulse width t wew 100 ns ce pulse width t cew 110 ns ce and ce2 pulse width t cew 110 ns data setup time t ds 80 ns data hold ti me t dh1 0 ns 8 data hold time t dh2 0 ns 9 address hold time t ah1 0 ns 8 address hold time t ah2 10 ns 9 we data off time t wez 40 ns write recovery time t wr 10 ns
ds1747/ds1747p y2k - compliant, nonvolatile timekeeping rams 12 of 16 write cycle timing diagram, write - enable controlled write cycle timing diagram, chip - enable controlled
ds1747/ds1747p y2k - compliant, nonvolatile timekeeping rams 13 of 16 power - up/down ac characteristics (5v) (v cc = 5.0v 10%, t a = over the operating range.) parameter symbol min typ max units notes ce or we at v h be fore power - down t pd 0 s v cc fall time: v pf(max) to v pf(min) t f 300 s v cc fall time: v pf(min) to v so t fb 10 s v cc rise time: v pf(min ) to v pf ( max) t r 0 s power - up recover time vpf to rst high (powercap only) t rec 35 ms expected data - r etention time (oscillator on) t dr 10 years 5, 6 power - up/down timing (5v device)
ds1747/ds1747p y2k - compliant, nonvolatile timekeeping rams 14 of 16 power - up/down characteristics (3.3v) (v cc = 3.3v 10%, t a = over the operating range.) parameter symbol min typ max units notes ce or we at v h , before power - down t pd 0 s v cc fall time: v pf(max) to v pf(min) t f 300 s v cc rise time: v pf(min) to v pf(max) t r 0 s power - up recover time v pf to rst high (powercap only) t rec 35 ms expected d ata - retention time (oscillator on) t dr 10 years 5, 6 power - up/down waveform timing (3.3v device) capacitance (t a = +25c) parameter symbol min typ max units notes capacitance on all input pins c in 14 pf capacitance on all output pins c o 10 pf
ds1747/ds1747p y2k - compliant, nonvolatile timekeeping rams 15 of 16 ac test conditions output load: 50 pf + 1ttl gate input pulse levels: 0 to 3.0v timing measurement reference levels: input: 1.5v output: 1.5v input pulse rise and fall times: 5ns notes: 1) voltages are referenced to ground. 2) typical values are at + 25 c and nominal supplies. 3) outputs are open. 4) battery switchover occurs at the lower of either the battery terminal voltage or v pf . 5) data - retention time is at +25 c. 6) each ds1747 has a built - in switch that disconnects the lithium source until the user first app lies v cc . the expected t dr is defined for dip modules and assembled powercap modules as accumulative time in the absence of v cc starting from the time power is first applied by the user. 7) rtc encapsulated dip (edip) modules can be successfully processed thr ough conventional wave - soldering techniques as long as temperatures as long as temperature exposure to the lithium energy source contained within does not exceed +85 c. post - solder cleaning with water - washing techniques is acceptable, provided that ultra - sonic vibration is not used. see the powercap package drawing on our website for details regarding the powercap package ( www.maxim - ic.com/ packages ). 8) t ah1 , t dh1 are measured from we going high. 9) t ah2 , t dh2 are measured from ce going high. 10) t wc = 200ns. package information for the latest package outline information and land patterns (footprints) , go to www.maxim - ic.com/packages . note that a +, #, or - in the package code indicates rohs status only. package drawings may show a different suffix character, but the drawing pertains to the package regardless of rohs status. package type package code outline no. land pattern no. 32 edip mdt32+4 21- 0245 34 pwrcp pc2+1 21- 0246
ds1747/ds1747p y2k - compliant, nonvolatile timekeeping rams 16 of 16 maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no cir cuit patent licenses are implied. maxim r eserves the right to change the circuitry and specifications without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408 - 737 - 7600 ? 201 2 maxim integrated products maxim is a registered trademark of maxim integrated products. revision history revision date description pages changed 9/10 updated the ordering information table top mark information and removed leaded parts; updated the absolute maximum ratings section to include the storage temperature range and lead and soldering temperatures for edip and powercap packages; added note 10 to the i cc parameter in the dc electrical characteristics tables (for 5.0v and 3.3v) and the notes section; updated the package information table 3, 8, 9, 15 3/12 updated the absolute ma ximum ratings section to add the 5v and 3.3v voltage range 8

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